Timing closure of nanometer designs now requires extensive timing coverage to meet yield predictions. Smaller device geometries have increased variability in manufacturing and second order effects, such as coupling, now play a significant role in signal integrity. To ensure that the design meets the required timing constraints, design engineers typically run statistical static timing analysis or make multiple timing runs at various modes and process conditions. Static timing analysis (STA) is one of the pillars for verifying digital Very Large Scale Integrated (VLSI) circuit designs, and is widely used to predict the performance of the designs. STA is often used on very large designs for which exhaustive timing analyses are impossible or impractical in view of the number of patterns required to perform the analysis. State of the art static timing analysis tools have the ability to model designs with multiple timing modes and multiple corners only in a single environment.                a. A timing engine allows separate timing constraints and extracted parasitics to be loaded for each timing corner, and controls are available to adjust the process conditions. The ability to model the timing of a design across the process space in a single environment allows users to examine problems for manual repair or allow an automated timing closure tool to fix the problem. The benefit of operating in such an environment is that logic and wire optimizations can immediately evaluate the effects of a potential fix across all analysis modes and corners, preventing the introduction of a new problem.        
The optimization of circuits in a multiple corner timing environment does have some drawbacks, however. The creation and initialization of multiple timing analysis modes consumes run time and increases process memory usage. Each additional timing model typically requires a separate timing graph which must be incrementally updated as netlist changes are made during the evaluation of fixes. The cost of incrementally updating the timing graph is further exacerbated when the timing environment employs high-accuracy timing modeling, such as rice delay calculation. The run time cost is also extended when running in a statistical static timing environment and all of these problems are further exacerbated by increasing the size of the design.
Referring to FIG. 1a, a flow chart is illustrated embodying a prior art multiple mode/multi-corner timing environment with timing closure, the timing closure in the illustrative environment being highly computer intensive.
Step 100 loads the design and any accompanying timing rules. Step 101 initializes the first timing analysis more or corner. Step 102 initializes a second timing analysis mode or corner. Step 103 performs automated timing closure that incrementally evaluates timing changes across both timing analyses performed in step 101 and 102. Although this approach allows tools to accurately fix timing problems, there is however a run-time cost associated with maintaining multiple timing models, rendering this approach inefficient and costly. When a tool makes a change to fix a problem the timing model for both STA graphs must be updated to allow the tool to evaluate whether the fix was sufficient. If the fix was not acceptable, another solution can be tried, or the tool may revert to its original implementation. In some cases, various optimizations can revisit the timing problem multiple times, and each change to the netlist requires the timing graph to be incrementally updated. Additionally there may thousands of timing problems to fix, and the cost of incrementally updating the design becomes prohibitive. The result is timing a closure tool that can run for many days, especially when run on large netlists.
Referring to FIG. 1b, a flow chart illustrates a problematic scenario encountered when attempting to initialize multi-mode/multi-corner STA in the prior art.
In certain instances, the prior art STA tool may not be able to load certain timing rules because of compatibility issues, or simultaneously handle certain types of assertions. In these situations, the user typically will optimize for a late mode timing closure and rerun the tool in another process environment to verify timing closure. This may expose problems in the current environment, and attempts to fix them could create problems in the original corner.
Still referring to FIG. 1b, in Step 110, the design is loaded along with any accompanying timing rules. In Step 111, the STA tool initializes a first static timing analysis corner for worst-case operating conditions. In step 112, the STA tool attempts to initialize a second static timing analysis corner for the best-case operating conditions. The attempt fails to initialize the timing graph because the best case (BC) timing rule is incompatible with the worst case (WC) timing rule.
Presently, the optimization of circuits for timing closure may require access to multiple analysis modes that are not available, or may be prohibitive to initialize. Furthermore, the tool may not allow the loading of timing rules under different characterization points, and the timing environment may be prohibitive for optimization (e.g., a high accuracy timing environment incurs an increased run time), and the chip timing with multiple analysis modes under a single process may exceed the machine memory limits.